Cache Access Counter enable and clear register
L2_IBUS0_CNT_ENA | The bit is used to enable ibus0 counter in L2-Cache. |
L2_IBUS1_CNT_ENA | The bit is used to enable ibus1 counter in L2-Cache. |
L2_IBUS2_CNT_ENA | Reserved |
L2_IBUS3_CNT_ENA | Reserved |
L2_DBUS0_CNT_ENA | The bit is used to enable dbus0 counter in L2-Cache. |
L2_DBUS1_CNT_ENA | The bit is used to enable dbus1 counter in L2-Cache. |
L2_DBUS2_CNT_ENA | Reserved |
L2_DBUS3_CNT_ENA | Reserved |
L2_IBUS0_CNT_CLR | The bit is used to clear ibus0 counter in L2-Cache. |
L2_IBUS1_CNT_CLR | The bit is used to clear ibus1 counter in L2-Cache. |
L2_IBUS2_CNT_CLR | Reserved |
L2_IBUS3_CNT_CLR | Reserved |
L2_DBUS0_CNT_CLR | The bit is used to clear dbus0 counter in L2-Cache. |
L2_DBUS1_CNT_CLR | The bit is used to clear dbus1 counter in L2-Cache. |
L2_DBUS2_CNT_CLR | Reserved |
L2_DBUS3_CNT_CLR | Reserved |