Espressif Systems /ESP32-C6 /EXTMEM /L2_CACHE_ACS_CNT_CTRL

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Interpret as L2_CACHE_ACS_CNT_CTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (L2_IBUS0_CNT_ENA)L2_IBUS0_CNT_ENA 0 (L2_IBUS1_CNT_ENA)L2_IBUS1_CNT_ENA 0 (L2_IBUS2_CNT_ENA)L2_IBUS2_CNT_ENA 0 (L2_IBUS3_CNT_ENA)L2_IBUS3_CNT_ENA 0 (L2_DBUS0_CNT_ENA)L2_DBUS0_CNT_ENA 0 (L2_DBUS1_CNT_ENA)L2_DBUS1_CNT_ENA 0 (L2_DBUS2_CNT_ENA)L2_DBUS2_CNT_ENA 0 (L2_DBUS3_CNT_ENA)L2_DBUS3_CNT_ENA 0 (L2_IBUS0_CNT_CLR)L2_IBUS0_CNT_CLR 0 (L2_IBUS1_CNT_CLR)L2_IBUS1_CNT_CLR 0 (L2_IBUS2_CNT_CLR)L2_IBUS2_CNT_CLR 0 (L2_IBUS3_CNT_CLR)L2_IBUS3_CNT_CLR 0 (L2_DBUS0_CNT_CLR)L2_DBUS0_CNT_CLR 0 (L2_DBUS1_CNT_CLR)L2_DBUS1_CNT_CLR 0 (L2_DBUS2_CNT_CLR)L2_DBUS2_CNT_CLR 0 (L2_DBUS3_CNT_CLR)L2_DBUS3_CNT_CLR

Description

Cache Access Counter enable and clear register

Fields

L2_IBUS0_CNT_ENA

The bit is used to enable ibus0 counter in L2-Cache.

L2_IBUS1_CNT_ENA

The bit is used to enable ibus1 counter in L2-Cache.

L2_IBUS2_CNT_ENA

Reserved

L2_IBUS3_CNT_ENA

Reserved

L2_DBUS0_CNT_ENA

The bit is used to enable dbus0 counter in L2-Cache.

L2_DBUS1_CNT_ENA

The bit is used to enable dbus1 counter in L2-Cache.

L2_DBUS2_CNT_ENA

Reserved

L2_DBUS3_CNT_ENA

Reserved

L2_IBUS0_CNT_CLR

The bit is used to clear ibus0 counter in L2-Cache.

L2_IBUS1_CNT_CLR

The bit is used to clear ibus1 counter in L2-Cache.

L2_IBUS2_CNT_CLR

Reserved

L2_IBUS3_CNT_CLR

Reserved

L2_DBUS0_CNT_CLR

The bit is used to clear dbus0 counter in L2-Cache.

L2_DBUS1_CNT_CLR

The bit is used to clear dbus1 counter in L2-Cache.

L2_DBUS2_CNT_CLR

Reserved

L2_DBUS3_CNT_CLR

Reserved

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